Shantian Qin

Shantian Qin

Ph.D. Candidate in Computer Architecture

Shantian Qin (秦善天)

I am currently a Ph.D. candidate at Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS), also with the University of Chinese Academy of Sciences (UCAS), advised by Prof. Wenming Li, Prof. Dongrui Fan, and Prof. Xiaochun Ye. Previously, I obtained my bachelor’s degree from Tongji University, advised by Prof. Meisong Tong (IEEE Fellow).

My research focuses on developing energy-efficient computer architectures via hardware-software co-design, with a special emphasis on data-intensive applications like emerging AI and big data analytics. My current interests include dataflow-driven AI chip design, reconfigurable computing, RISC-V ISA extensions, and memory-centric computing.

🔥 News

  • [2026/03] One paper is accepted by DAC 2026!🎉
  • [2026/02] Invited to serve as the PC Member of IEEE MCSoC 2026.
  • [2026/01] Awarded the Outstanding Student of State Key Laboratory of Processors!🏆
  • [2025/11] Awarded the Best Presentation Award at UCAS Academic Forum 2025!🏆
  • [2025/11] One paper is accepted by DATE 2026!🎉
  • [2025/11] Invited to serve as the Reviewer of IEEE ISCAS 2026.
  • [2025/11] Awarded the National Scholarship 国家奖学金!🏆
  • [2025/07] Giving a talk on Edge-AI Dataflow Accelerators at CCF Computility 2025.
  • [2025/05] Awarded the Pacemaker to Merit Student 三好学生标兵 of UCAS!🏆
  • [2025/02] One paper is accepted by ACM TACO!🎉
  • [2025/01] One paper is accepted by IEEE ISCAS 2025!🎉
  • [2024/12] Awarded the HYGON Scholarship 海光奖学金 of ICT-CAS & HYGON!🏆

📝 Selected Publications

Patents

  • 李文明, 范志华, 秦善天, 叶笑春, 孙凝晖. 一种面向异构智能数据流模型的程序执行方法及装置. CN202511335451.5, 2025.
  • 秦善天, 李文明, 范志华, 安学军, 叶笑春. 一种数据流架构的半集中式动态任务调度装置及方法. CN202510890805.6, 2025.
  • 秦善天, 李文明, 范志华, 安学军, 叶笑春, 范东睿. 一种数据流众核处理器的数据预取方法及处理器. CN202410263613.8, 2024.

🎓 Education

Sep. 2023 - Present: Institute of Computing Technology, Chinese Academy of Sciences

Sep. 2019 - Jul. 2023: Tongji University

  • National Demonstration School of Microelectronics
  • B.Eng. in Electronic Science and Technology (Microelectronics)
  • Advisor: Prof. Meisong Tong (IEEE Fellow)
  • GPA: 90/100, First-Class Outstanding Undergraduate Scholarship (top 5%, 2021-2022)

👨‍🏫 Services

Academic Services

  • IEEE MCSoC (Multicore/Many-core Systems-on-Chip), 2026, PC Member
  • IEEE ISCAS, 2026, Reviewer (CCF B)
  • Parallel Computing (PARCO), 2025, Sub-Reviewer (CCF B)
  • Future Generation Computer Systems (FGCS), 2025, Sub-Reviewer (JCR Q1)
  • Sustainable Computing: Informatics & Systems (SUSCOM), 2025, Sub-Reviewer (JCR Q1)
  • The Journal of Supercomputing (TJSC), 2025, Sub-Reviewer (JCR Q2)
  • IEEE ISPA, 2025, Sub-Reviewer (CCF C)
  • CCF HPC China, 2025, Sub-Reviewer (Academic Annual Conf. of CCF TC-HPC)
  • CCF NCCET, 2025, Sub-Reviewer (Academic Annual Conf. of CCF TC-CET)

Professional Affiliations

  • Graduate Student Member: IEEE (IEEE CS, IEEE CASS, IEEE CEDA), ACM, CCF

Volunteer Services and Leaderships

  • Vice President and Head of the Popular Science Department of Student Association for Science and Technology, ICT-CAS, 2024-Present
  • Member of the Executive Committee of Student Union, Tongji University, 2021-2022

🏅 Honors and Awards

  • Outstanding Student of State Key Laboratory of Processors, 2025
  • Best Presentation Award at UCAS Graduate Academic Forum 2025
  • National Scholarship 国家奖学金 (top 0.4%), Ministry of Education, PRC, 2025
  • Pacemaker to Merit Student 三好学生标兵 (top 1%), UCAS, 2025
  • HYGON Scholarship 海光奖学金 (2/200+), ICT-CAS & HYGON, 2024
  • First-Class Graduate Academic Scholarship, UCAS, 2023-2025
  • First-Class Outstanding Undergraduate Scholarship (top 5%), Tongji University, 2021-2022
  • Gold Award at National Final 全国金奖, 13th “Challenge Cup” Competition, 2023
  • Silver Award at National Final 全国银奖, 7th “Internet+” Competition, 2021

🎤 Invited Talks

  • Optimizing Data Access–Flow–Processing Scheduling in Dataflow Architectures for Edge High-Throughput Applications via Hardware-Software Co-Design
    UCAS Graduate Academic Forum 2025, Beijing, China, Nov. 2025
  • Research on Decentralized Task Scheduling for Edge Intelligence Accelerators
    CCF Computility 2025 (Excellent PhD & Young Scholar Forum), Lanzhou, China, Jul. 2025
  • StreamDCIM: A Tile-Based Streaming Digital CIM Accelerator with Mixed-Stationary Cross-Forwarding Dataflow for Multimodal Transformer
    IEEE ISCAS 2025 (Conference Talk), London, United Kingdom, May 2025
  • ROMA: A Reconfigurable On-Chip Memory Architecture for Multi-Core Accelerators
    IEEE HPCC 2023 (Conference Talk), Melbourne, Australia, Dec. 2023

🔍 Research Experiences

My research focuses on Hardware-Software Co-Design of Dataflow-Driven Execution Model for Emerging AI Applications, with the following directions:

  • Dataflow-Driven Data Prefetching
  • Dataflow-Driven Task Scheduling
  • Dataflow-Driven RISC-V Extensions
  • Dataflow-Driven In-Memory Computing

I aim to optimize dataflow-driven data prefetching, task scheduling, in-memory computing, and RISC-V extension via Algorithm-Architecture-Circuit Co-Design for emerging AI, cryptography, and graph applications, particularly in accelerating sparse scenarios.

Dataflow-Driven RISC-V Extensions

  • [DATE’26] RISC-V ISA Extensions for Unstructured Sparse SpMM in LLM Inference

Dataflow-Driven Task Scheduling

  • [Under Review] Dynamic Scheduling Ideal Paradigm for Dataflow Architecture
  • [ACM TACO’25] PANDA: Decentralized Dataflow PE and Distributed Task Scheduling

Dataflow-Driven In-Memory Computing

  • [IEEE ISCAS’25] StreamDCIM: Tile-Based Streaming Digital CIM for Multimodal Transformer

Dataflow-Driven Data Prefetching

  • [IEEE HPCC’23] ROMA: Reconfigurable On-Chip Memory Architecture

🧑‍💻 Industry Experiences

SmarCo (中科睿芯) (Feb. 2023 - Present)

  • Research Intern in Processor Architecture Group, supervised by Prof. Wenming Li
  • Overview: Dataflow-Driven AI Accelerator and RISC-V Processor Chip Design
    • RTL: ScratchPad Memory and Cache reusable on-chip memory implementation
    • Simulator: Processing Element (Tensor Core) & On-Chip Memory (Data Buffer) & Data Transfer (INT8/FP16 Matrix Normal/Transpose Mode) optimization, SIMD/Logic & Load/Store instructions exetension
    • Runtime: Runtime design for multi-application dynamic scheduling

AMD (Undergraduate Internship)

  • Intern in Xilinx HLS Software Department, mentored by Dr. Yuanjie Huang and Tuo Lin
  • Development of hardware-accelerated open-source libraries for Xilinx FPGA and Versal ACAP hardware platforms

✉️ Contact

  • Email: qinshantian23s [at] ict [dot] ac [dot] cn
  • Address: Building 1, Institute of Computing Technology, Chinese Academy of Sciences, Environmental Science and Technology Park, Beiqing Road, Haidian District, Beijing, China