Shantian Qin (秦善天)

I am a Ph.D. candidate at the Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS), also with the University of Chinese Academy of Sciences (UCAS), advised by Prof. Wenming Li, Prof. Dongrui Fan, and Prof. Xiaochun Ye. Previously, I received my bachelor’s degree from Tongji University, advised by Prof. Meisong Tong (IEEE Fellow), and also interned at AMD and SmarCo’s Processor Architecture Group.

My research focuses on developing energy-efficient computer architectures through hardware-software co-design and innovative computing paradigms. My current interests include dataflow architecture, reconfigurable computing, memory-centric computing, and RISC-V ISA extensions, targeting high-throughput computing and emerging AI applications like large language models (LLMs) and vision-language models (VLMs).

🔥 News

📝 Selected Publications

• A Scalable RISC-V Extended Infrastructure for Unstructured SpMM in LLM Inference with Vectorizable Sparse Format
  T. Xia, Z. Fan, J. Xue, T. Luo, S. Qin, X. Ye, D. Fan, W. Li
  IEEE TCAD, 2026, Just Accept (CCF A)
• UniNL: Unifying Fragmented Non-Linear Operators for Efficient Edge LLM Inference
  Z. Hu, Z. Fan, S. Qin, Y. Mu, W. Li, X. Ye
  DAC 2026, Long Beach, CA, USA, 2026, pp. 1-7 (CCF A)
• RISC-V ISA Extensions for Vectorized Unstructured Sparse SpMM in LLM Inference
  T. Xia, Z. Fan, J. Xue, S. Qin, W. Li, X. Ye
  DATE 2026, Verona, Italy, 2026, pp. 1-7 (CCF B)
• PANDA: Adaptive Prefetching and Decentralized Scheduling for Dataflow Architectures
  S. Qin, Z. Fan, W. Li, Z. Wang, X. An, X. Ye, D. Fan
  ACM TACO, 2025, vol. 22, no. 2, article 62, pp. 1-27 (CCF A)
• StreamDCIM: A Tile-Based Streaming Digital CIM Accelerator with Mixed-Stationary Cross-Forwarding Dataflow for Multimodal Transformer
  S. Qin, Z. Qiang, Z. Fan, W. Li, X. An, X. Ye, D. Fan
  IEEE ISCAS 2025, London, United Kingdom, 2025, pp. 1-5 (CCF B)
• ROMA: A Reconfigurable On-Chip Memory Architecture for Multi-Core Accelerators
  S. Qin, W. Li, Z. Fan, Z. Wang, T. Liu, H. Wu, K. Zhang, X. An, X. Ye, D. Fan
  IEEE HPCC 2023, Melbourne, Australia, 2023, pp. 49-57 (CCF C)

Patents

• 李文明, 范志华, 秦善天, 叶笑春, 孙凝晖. 一种面向异构智能数据流模型的程序执行方法及装置. CN202511335451.5, 2025.
• 秦善天, 李文明, 范志华, 安学军, 叶笑春. 一种数据流架构的半集中式动态任务调度装置及方法. CN202510890805.6, 2025.
• 秦善天, 李文明, 范志华, 安学军, 叶笑春, 范东睿. 一种数据流众核处理器的数据预取方法及处理器. CN202410263613.8, 2024.

🎓 Education

Sep. 2023 - Present: Institute of Computing Technology, Chinese Academy of Sciences

• State Key Laboratory of Processors
• Ph.D. in Computer Science and Technology (Computer Architecture)
• Advisor: Prof. Wenming Li, Prof. Dongrui Fan, and Prof. Xiaochun Ye
• GPA: 3.93/4, National Scholarship (top 0.4%), Pacemaker to Merit Student (top 1%)

Sep. 2019 - Jul. 2023: Tongji University

• National Demonstration School of Microelectronics
• B.Eng. in Electronic Science and Technology (Microelectronics)
• Advisor: Prof. Meisong Tong (IEEE Fellow), who supervised my undergraduate research leading to a paper published at ACES 2022 (CIE Class I Conference)
• GPA: 90/100, First-Class Outstanding Undergraduate Scholarship (top 5%, 2021-2022)

👨‍🏫 Services

Academic Services

• IEEE MCSoC (Multicore/Many-core Systems-on-Chip), 2026, PC Member
• IEEE ISCAS, 2026, Reviewer (CCF B)
• IEEE APCCAS, 2026, Reviewer
• Parallel Computing (PARCO), 2025, Sub-Reviewer (CCF B)
• Future Generation Computer Systems (FGCS), 2025, Sub-Reviewer (JCR Q1)
• Sustainable Computing: Informatics & Systems (SUSCOM), 2025, Sub-Reviewer (JCR Q1)
• The Journal of Supercomputing (TJSC), 2025, Sub-Reviewer (JCR Q2)
• IEEE ISPA, 2025, Sub-Reviewer (CCF C)
• CCF HPC China, 2025, Sub-Reviewer (Academic Annual Conf. of CCF TC-HPC)
• CCF NCCET, 2025, Sub-Reviewer (Academic Annual Conf. of CCF TC-CET)

Professional Affiliations

• Graduate Student Member: IEEE (IEEE CS, IEEE CASS, IEEE CEDA), ACM, CCF

Volunteer Services and Leaderships

• Vice President and Head of the Popular Science Department of Student Association for Science and Technology, ICT-CAS, 2024-Present
• Member of the Executive Committee of Student Union, Tongji University, 2021-2022

🏅 Honors and Awards

• Outstanding Student Leader 优秀学生干部 (top 2%), UCAS, 2026
• Best Presentation Award at UCAS Graduate Academic Forum 2025
• Outstanding Student of State Key Laboratory of Processors, 2025
• National Scholarship 国家奖学金 (top 0.4%), Ministry of Education, PRC, 2025
• Pacemaker to Merit Student 三好学生标兵 (top 1%), UCAS, 2025
• HYGON Scholarship 海光奖学金 (2/200+), ICT-CAS & HYGON, 2024
• First-Class Graduate Academic Scholarship, UCAS, 2023-2025
• First-Class Outstanding Undergraduate Scholarship (top 5%), Tongji University, 2021-2022
• Gold Award at National Final 全国金奖, 13th “Challenge Cup” Competition, 2023
• Silver Award at National Final 全国银奖, 7th “Internet+” Competition, 2021

🎤 Invited Talks

• Optimizing Data Access–Flow–Processing Scheduling in Dataflow Architectures for Edge High-Throughput Applications via Hardware-Software Co-Design
  UCAS Graduate Academic Forum 2025, Beijing, China, Nov. 2025
• Research on Decentralized Task Scheduling for Edge Intelligence Accelerators
  CCF Computility 2025 (Excellent PhD & Young Scholar Forum), Lanzhou, China, Jul. 2025
• StreamDCIM: A Tile-Based Streaming Digital CIM Accelerator with Mixed-Stationary Cross-Forwarding Dataflow for Multimodal Transformer
  IEEE ISCAS 2025 (Conference Talk), London, United Kingdom, May 2025
• ROMA: A Reconfigurable On-Chip Memory Architecture for Multi-Core Accelerators
  IEEE HPCC 2023 (Conference Talk), Melbourne, Australia, Dec. 2023

🧑‍💻 Industry Experiences

中科睿芯 (2023 - Present)

• Intern in Processor Architecture Group, supervised by Prof. Wenming Li
• Overview: Dataflow-Driven AI Accelerator and RISC-V Processor Chip Design
  • RTL: ScratchPad Memory and Cache reusable on-chip memory implementation
  • Simulator: Processing Element (Tensor Core) & On-Chip Memory (Data Buffer) & Data Transfer (INT8/FP16 Matrix Normal/Transpose Mode) optimization, SIMD/Logic & Load/Store instruction extensions
  • Runtime: Runtime design for multi-application dynamic scheduling

超威半导体 (2022 - 2023)

• Intern in Xilinx HLS Software Department, mentored by Dr. Yuanjie Huang and Tuo Lin
• Development of hardware-accelerated open-source libraries for Xilinx FPGA and Versal ACAP hardware platforms

✉️ Contact

• Email: qinshantian23s [at] ict [dot] ac [dot] cn
• Address: Building 1, Institute of Computing Technology, Chinese Academy of Sciences, Environmental Science and Technology Park, Beiqing Road, Haidian District, Beijing, China