Shantian Qin (秦善天)
Welcome! I am currently a third-year Ph.D. student at Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS), also with the University of Chinese Academy of Sciences (UCAS), advised by Prof. Wenming Li and Prof. Dongrui Fan. Previously, I obtained my bachelor’s degree from the School of Microelectronics, Tongji University. My research interests include dataflow-driven AI chip design, reconfigurable computing, memory-centric computing, and hardware-software co-design. Please feel free to contact me.
🔥 News
- [2025/07] Giving a talk on Edge-AI Dataflow Accelerators in CCF Computility 2025.
- [2025/05] Awarded the Pacemaker to Merit Students of UCAS!🏆
- [2025/02] One paper is accepted by ACM TACO! Congratulations to all!🎉
- [2025/01] One paper is accepted by IEEE ISCAS 2025! Congratulations to all!🎉
- [2024/12] Awarded the HYGON Named Scholarship of ICT-CAS & HYGON!🏆
🎓 Education
Sep. 2023 - Present: Institute of Computing Technology, Chinese Academy of Sciences
- State Key Laboratory of Processors
- Ph.D. in Computer Science and Technology (Computer Architecture)
- Advisor: Prof. Wenming Li and Prof. Dongrui Fan
- GPA: 3.94/4, Pacemaker to Merit Students (top 1%), HYGON Scholarship (2/200+, 2024)
Sep. 2019 - Jul. 2023: Tongji University
- National Demonstration School of Microelectronics
- B.Eng. in Electronic Science and Technology (Microelectronics)
- Advisor: Prof. Meisong Tong (IEEE AP-S Distinguished Lecturer, EMA/JSPS Fellow)
- GPA: 90/100, First Prize Scholarship for Outstanding Students (top 5%, 2021-2022)
🔍 Research Experiences
My research focuses on Hardware-Software Co-Design of Dataflow-Driven Execution Model for Emerging AI Applications, with the following directions:
- Dataflow-Driven Data Prefetching
- Dataflow-Driven Task Scheduling
- Dataflow-Driven In-Memory Computing
I aim to optimize dataflow-driven data prefetching, task scheduling, in-memory computing, and RISC-V extension via Algorithm-Architecture-Circuit Co-Design for emerging AI, cryptography, and graph applications, particularly in accelerating sparse scenarios.
Dataflow-Driven Task Scheduling
- [Under Review] Dynamic Scheduling Ideal Paradigm for Dataflow Architecture
- [ACM TACO’25] PANDA: Decentralized Dataflow PE and Distributed Task Scheduling
Dataflow-Driven In-Memory Computing
- [IEEE ISCAS’25] StreamDCIM: Tile-Based Streaming Digital CIM for Multimodal Transformer
Dataflow-Driven Data Prefetching
- [IEEE HPCC’23] ROMA: Reconfigurable On-Chip Memory Architecture
🧑💻 Industry Experiences
SmarCo (中科睿芯) (Feb. 2023 - Present)
- Research Intern in Processor Architecture Group, supervised by Prof. Wenming Li
- Overview: Dataflow-Driven AI Accelerator and RISC-V Processor Chip Design
- RTL: ScratchPad Memory and Cache reusable on-chip memory implementation
- Simulator: Processing Element (Tensor Core) & On-Chip Memory (Data Buffer) & Data Transfer (INT8/FP16 Matrix Normal/Transpose Mode) optimization, SIMD/Logic & Load/Store instructions exetension
- Runtime: Runtime design for multi-application dynamic scheduling
AMD (Undergraduate Internship)
- Intern in Xilinx HLS Software Department, mentored by Dr. Yuanjie Huang and Tuo Lin
- Development of hardware-accelerated open-source libraries for Xilinx FPGA and Versal ACAP hardware platforms
📝 Selected Publications
- PANDA: Adaptive Prefetching and Decentralized Scheduling for Dataflow Architectures
S. Qin, Z. Fan, W. Li, Z. Wang, X. An, X. Ye, D. Fan
ACM TACO, 2025, vol. 22, no. 2, pp. 1-27 (CCF A) - StreamDCIM: A Tile-Based Streaming Digital CIM Accelerator with Mixed-Stationary Cross-Forwarding Dataflow for Multimodal Transformer
S. Qin, Z. Qiang, Z. Fan, W. Li, X. An, X. Ye, D. Fan
IEEE ISCAS 2025, London, United Kingdom, 2025, pp. 1-5 (TH-CPL B) - ROMA: A Reconfigurable On-Chip Memory Architecture for Multi-Core Accelerators
S. Qin, W. Li, Z. Fan, Z. Wang, T. Liu, H. Wu, K. Zhang, X. An, X. Ye, D. Fan
IEEE HPCC 2023, Melbourne, Australia, 2023, pp. 49-57 (CCF C)
📑 Patents
- 李文明, 范志华, 秦善天, 叶笑春, 孙凝晖. 一种面向异构智能数据流模型的程序执行方法及装置. Application No. 202511335451.5, 2025.
- 秦善天, 李文明, 范志华, 安学军, 叶笑春. 一种数据流架构的半集中式动态任务调度装置及方法. Application No. 202510890805.6, 2025.
- 秦善天, 李文明, 范志华, 安学军, 叶笑春, 范东睿. 一种数据流众核处理器的数据预取方法及处理器. Publication No. CN118132462A, 2024.
🏅 Honors and Awards
- Pacemaker to Merit Students (top 1%), UCAS, 2025
- HYGON Named Scholarship (2/200+), ICT-CAS & HYGON, 2024
- First Prize in Academic Scholarship, UCAS, 2023-2024
- First Prize Scholarship for Outstanding Students (top 5%), Tongji University, 2021-2022
- First Prize (Gold Award) at National Final, 13th “Challenge Cup” Competition, 2023
- Second Prize (Silver Award) at National Final, 7th “Internet+” Competition, 2021
👨🏫 Services
Academic Services
- Sub-Reviewer: IEEE ISPA 2025, HPC China 2025, CCF NCCET 2025, Future Generation Computer Systems, Sustainable Computing: Informatics and Systems
Professional Affiliations
- Graduate Student Member: IEEE (IEEE CS, IEEE CASS, IEEE CEDA), ACM, CCF
Volunteer Services and Leaderships
- Head of the Popular Science Department of Student Association for Science and Technology, ICT-CAS, 2024-Present
- Member of the Executive Committee of Student Union, Tongji University, 2021-2022
🎤 Invited Talks
- Research on Decentralized Task Scheduling for Edge Intelligence Accelerators
CCF Computility 2025 (Young Scholar & Excellent PhD Forum), Lanzhou, China, Jul. 2025 - StreamDCIM: A Tile-Based Streaming Digital CIM Accelerator with Mixed-Stationary Cross-Forwarding Dataflow for Multimodal Transformer
IEEE ISCAS 2025 (Conference Talk), London, United Kingdom, May 2025 - ROMA: A Reconfigurable On-Chip Memory Architecture for Multi-Core Accelerators
IEEE HPCC 2023 (Conference Talk), Melbourne, Australia, Dec. 2023
✉️ Contact
- Email: qinshantian23s [at] ict [dot] ac [dot] cn
- Address: Building 1, Institute of Computing Technology, Chinese Academy of Sciences, Environmental Science and Technology Park, Beiqing Road, Haidian District, Beijing, China